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mitsumi ic for cmos system reset pst4xxaxxxn ic for cmos system reset monolithic ic pst4xxaxxxn series outline this is a system reset ic developed using the cmos process. the cmos process allows ultra-low current consumption of 1.5?(typ.). further, a fixed delay timer is built in, so that supply voltage is verified when the power is turned on or interrupted to reset the system accurately. features 1. detection voltage accuracy ?.5% (25?, v dd = v det + 0.1) 2. low current consumption sot-23 : 1.5? 3. no external capacitor for delay timer required built-in delay timer sot-23 : 50/100/200/240/400ms 4. enhanced rank lineup available for detection voltage, package, output configuration and delay timer. 5. operating temperature range supporting automotive devices -40 ~ +105?. package sot-23a applications 1. reset circuits for microcomputers, cpus and mpus 2. reset circuits for logic circuits 3. battery voltage check circuits 4. back-up power supply switching circuits 5. level detection circuits 6. mechanical reset circuits pin assignment 12 3 sot-23a 1 gnd 2 v out 3 v dd
mitsumi ic for cmos system reset pst4xxaxxxn block diagram pin explanations v dd v out timer gnd v dd v out timer gnd pst41 a n active-low output pst43 a n active-high output v dd v out timer gnd v dd v out timer gnd pst42 a n active-low output pst44 a n active-high output cmos output n-ch open drain output pin explanations ab df output type t del rank v det rank packing specifications 1 cmos output 1 50ms 160 v det =1.60v r r housing active-low output 2 n-ch open drain output 2 100ms l l housing active-low output 3 cmos output 3 200ms 480 v det =4.80v active-high output 4 n-ch open drain output 4 240ms active-high output 5 400ms pst4 a n ab d f ~ ~ pin no. pin name function 1 gnd gnd pin 2 v out reset signal output pin 3 v dd power supply pin/voltage detect pin
mitsumi ic for cmos system reset pst4xxaxxxn absolute maximum ratings (ta=25?) recommended operating conditions item symbol rating unit operating temperature t opr - 40 ~ +105 c storage temperature t stg - 65 ~ +160 c supply voltage v dd max. 6.5 v output voltage v out gnd - 0.3 ~ vdd max.+0.3(cmos type) v gnd - 0.3 ~ 6.5(n-ch open drain type) output current i out 20 ma power dissipation p d 150 mw item symbol rating unit operating temperature t opr - 40 ~ +105 c
mitsumi ic for cmos system reset pst4xxaxxxn electrical characteristics (unless otherwise specified, ta=25?) item symbol test conditions min. typ. max. unit v dd range v dd test circuit 1 1.0 6.0 v detecting voltage v det test circuit 1 - 1.5% 1.6v~4.8v +1.5% v (0.1v step) detecting voltage temp. coefficient v det / t - 40?c < < = t opr < < = 105?c test circuit1 ?0 ppm/?c supply curren ti ss v dd =v det +0.1 test circuit 2 1.5 3.5 ? pst4 160n ~ v dd =v det - 0.1v pst4 230n i out =150? "h" out put voltage pst4 240n ~ v dd =v det - 0.1v (pst41 a /42 a) v oh pst4 350n i out =500? 0.8v dd v pst4 360n ~ v dd =v det - 0.1v pst4 480n i out =800? test circuit 6 pst4 160n ~ v dd =v det +0.1v 0.3 v "l" out put voltage pst4 350n i out =1.2ma (pst41 a /42 a) v ol pst4 360n ~ v dd =v det +0.1v pst4 480n i out =3.2ma 0.4 v test circuit 7 pst4 160n ~ v dd =v det +0.1v pst4 230n i out =150? "h" out put voltage pst4 240n ~ v dd =v det +0.1v (pst43 a /44 a) v oh pst4 350n i out =500? 0.8v dd v pst4 360n ~ v dd =v det +0.1v pst4 480n i out =800? test circuit 6 pst4 160n ~ v dd =v det - 0.1v 0.3 v "l" out put voltage pst4 350n i out =1.2ma (pst43 a /44 a) v ol pst4 360n ~ v dd =v det - 0.1v pst4 480n i out =3.2ma 0.4 v test circuit 7 35 50 65 70 100 130 reset active timeout period t del test circuit 8 140 200 260 ms 170 240 310 280 400 520 v dd to reset delay t det test circuit 8 20 s output leakage current i leak test circuit 5 0.1 ? (pst42 a /44 a) note 1: this device is tested at only normal temperature. over temperature limit guaranteed by desigh only. note 2: this device has no hysteresis voltage.
mitsumi ic for cmos system reset pst4xxaxxxn (1)-a pst41 a / 43 a v in v dd pst 4 a 2 3 1 gnd out (1)-b pst42 a / 44 a pst 4 a v in v dd 2 3 1 gnd out rl (2) pst 4 a v dd 3 1 2 i ss v in gnd (3) pst 4 a out i sink v ds 2 3 1 v dd gnd v in (4) pst 4 a out i source v ds 2 3 1 v dd gnd v in (5) pst 4 a out i leak v ds 2 3 1 v dd gnd v in measuring circuit
mitsumi ic for cmos system reset pst4xxaxxxn measuring circuit (6) pst 4 a out i oh v oh 2 3 1 v dd gnd v in v (7) pst 4 a out i ol v ol 2 3 1 v dd gnd v in v (8) pst41 a / 43 a v in v dd pst 4 a 2 3 1 gnd out (9) pst42 a / 44 a pst 4 a v in v dd 2 3 1 gnd out r l =470k ? input voltage output voltage pst41 a pst42 a output voltage pst43 a pst44 a v det +1.0v v det 1.0v gnd gnd 100% 50% gnd 100% 50% t del t det t del delay time t det
mitsumi ic for cmos system reset pst4xxaxxxn application circuits v dd gnd v out 3 1 2 pst 4 a v dd reset logic system v in please note that there is any possibility of circuit oscillation when resistance put in the line vin. load current and load resistance should be adjusted, which not over power dissipation level. pd>(v dd - v oh ) ?i oh pd> v ol ?i ol we shall not be liable for any trouble or damage caused by using this circuit. in the event a problem which may affect industrial property or any other rights of us or a third party is encountered during the use of information described in these circuit, mitsumi electric co., ltd. shall not be liable for any such problem, nor grant a license therefore. pst 4 a v in v dd out 1 3 2 gnd
mitsumi ic for cmos system reset pst4xxaxxxn timing chart v v v dd v out v det t del t del pst41 a / 42 a active-low output v v v dd v out v det t del t del pst43 a / 44 a active-high output
mitsumi ic for cmos system reset pst4xxaxxxn detecting voltage (pst414a290n ) 0 0 0.5 1 1.5 2 2.5 3 3.5 * 4 3 2 1 output voltage (v) input voltage (v) detecting voltage (pst434a290n ) 0 0 0.5 1 1.5 2 2.5 3 3.5 * 4 3 2 1 output voltage (v) input voltage (v) supply current 0 012345 2.5 2 1.5 1 0.5 v det =2.90v v det =4.60v input voltage (v) supply current ( a) n-ch output current (pst414a460n ) v dd =1v v dd =2v 0 0 0.5 1.5 123 2.5 4 3.5 60 50 40 30 20 10 v dd =4v v dd =3v v ds (v) n-ch output current (ma) p-ch output current (pst414a290n ) 0 012 4 35 60 50 40 30 20 10 v dd =5v v dd =4v v dd =3v v dd -v ds (v) p-ch output current (ma) note: these are typical characteristics. characteristics test circuit 1-b (r l =12k ? ) * when input voltage is under 1.0v, output voltage is unstable. test circuit 1-b (r l =12k ? ) test circuit 2 test circuit 3 test circuit 4
mitsumi ic for cmos system reset pst4xxaxxxn detecting voltage vs temperature (pst414a290n ) 2.87 - 40 - 20 20 080 60 40 100 2.93 2.92 2.91 2.90 2.89 2.88 temperature ( c) detecting voltage (v) supply current vs temperature (pst414a290n ) 0 - 40 - 20 20 080 60 40 100 4 3 2 1 supply current ( a) temperature ( c) threshold operating voltage vs temperature 0.6 - 40 - 20 20 080 60 40 100 1.2 1.1 1.0 0.9 0.7 0.8 temperature ( c) threshold operating voltage (v) output leakage current vs temperature 0 - 40 - 20 20 080 60 40 100 20 10 5 15 temperature ( c) output leakage current (na) reset active timeout period vs temperature 150 - 40 - 20 20 080 60 40 100 350 250 200 300 temperature ( c) reset active timeout period (ms) v dd to reset delay vs temperature 0 - 40 - 20 20 080 60 40 100 50 20 10 40 30 temperature ( c) v dd to reset delay ( s) note: these are typical characteristics. characteristics test circuit 1-a test circuit 2 test circuit 7 test circuit 5 test circuit 8 test circuit 8
mitsumi ic for cmos system reset pst4xxaxxxn "h"output voltage vs temperature (pst414a290n ) 2.80 - 40 - 20 20 080 60 40 100 3.00 2.90 2.85 2.95 output voltage (v) temperature ( c) "l"output voltage vs temperature (pst414a290n ) 0.00 - 40 - 20 20 080 60 40 100 0.50 0.20 0.10 0.40 0.30 output voltage (v) temperature ( c) maximum transient duration vs v det -v dd v det =4.60v v det =2.90v 0 11 0 100 1000 250 150 50 100 200 maximum transient duration ( s) v det -v dd (mv) reset active timeout period vs v dd -v det (pst414a290n ) 150 01 3 24 350 250 200 300 reset active timeout period (ms) v dd -v det (v) note: these are typical characteristics. test circuit 6 test circuit 7 test circuit 8 test circuit 8 characteristics

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